1. Field of the Invention
The present invention relates to an anti-fuse circuit and a semiconductor device including the same, and, more particularly relates to an anti-fuse circuit capable of performing a writing operation to an anti-fuse element at high speed and a semiconductor device including the same. The present invention also relates to a method of writing an address to such an anti-fuse circuit.
2. Description of Related Art
In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a defective cell that does not operate properly is replaced by a redundant cell to repair a defective address. In storing the defective address, generally, a fuse element is used (see Japanese Patent Application Laid-open Nos. H10-75170 and 2006-147651). The fuse element in an initial state is electrically conductive. When the fuse element is cut by a laser-beam irradiation, the defective address can be stored in a nonvolatile manner. Accordingly, when a plurality of such fuse elements are arranged to cut a desired fuse element, it becomes possible to store a desired address. Thus, the conventional fuse element stores information in a nonvolatile manner by changing from a conductive state to an insulating state.
On the other hand, recently, an element called an anti-fuse element gains a focus of attention (Japanese Patent Application Laid-open No. 2004-227361). Contrary to the conventional fuse element, the anti-fuse element stores the information by changing from the insulating state to the conductive state. Writing of the information to the anti-fuse element is performed by dielectric breakdown caused by applying a high voltage. Thus, unlike the conventional fuse element, the laser-beam irradiation is not necessary when writing. This leads to a high-speed writing of the defective address and eliminates an apparatus such as a laser trimmer. In addition, breaking of a passivation film resulting from the laser-beam irradiation does not occur, and therefore product reliability can also be increased.
The writing of the defective address to the anti-fuse element is performed after an operation test in a wafer state. The operation test in a wafer state is not performed on each chip, but generally, the test is performed on a plurality of chips in parallel. That is, when a clock terminal, an address terminals, and a command terminals are each commonly connected among a plurality of chips, which are subject to the test, a clock signal, an address signal, and a command signal common to these chips are applied, and in this state, a data writing or a data reading is actually performed. At least output data need to be individual for each chip, and therefore, needless to say, a data input/output terminal is not commonly connected.
As described above, at a time of the operation test in a wafer state, the address terminals are commonly connected among the chips, which are subject to test, and due to this reason, an individual address cannot be supplied to each chip. However, needles to say, the detected defective address differs depending on each chip. Accordingly, it is necessary to perform the writing operation of the defective address individually on each chip, and therefore the writing operation cannot be performed in parallel. That is, while the operation test can be performed in parallel for the chips, the writing operation of the defective address has to be individually performed on each chip.
The writing operation of the defective address to the anti-fuse circuit can be performed at higher speed as compared to the writing operation of the defective address to the fuse element by laser-beam irradiation. However, the writing to the anti-fuse circuit is performed by the dielectric breakdown caused by applying the high voltage, and therefore, as compared to normal data input/output, it takes a very long time. As one example, when there are 1000 fuse sets each capable of storing one defective address and a writing time for one fuse set is 5 milliseconds (ms), it requires about 5 seconds per chip to perform writing to all the fuse sets.
A resistance of the anti-fuse element that undergoes the dielectric breakdown greatly deviates depending on a level of the dielectric breakdown or a generation location. Therefore, in some cases, there is a case that the resistance after the dielectric breakdown is in the order of megaohms (MΩ). In this case, it becomes difficult to determine whether the anti-fuse element is broken. However, in a fuse set in which the writing of the defective address is once performed, an enable fuse indicating whether the fuse set is used is also broken, and therefore this fuse set cannot be restored to an unused state. There arises a problem that when the writing of the defective address is unsuccessful, the entire chip needs to be abandoned.